The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly relates to a technique effectively applied to a semiconductor device including a fin transistor.
A fin field effect transistor is known as a field effect transistor that has a high operation speed, and allows a reduction in leakage current, power consumption, and size. The fin field effect transistor (FINFET) is, for example, a semiconductor element that has a channel layer including a pattern of a plate-like (wall-like) semiconductor layer protruding on a substrate, and has a gate electrode formed so as to straddle the pattern.
The electrically erasable and programmable read only memory (EEPROM) is widely used as an electrically writable and erasable, nonvolatile semiconductor memory device. Such memory devices typified by a currently widely used flash memory each have a conductive floating gate electrode surrounded by an oxide film or a trapping insulating film below a gate electrode of a MISFET, and a charge accumulation state in the floating gate or the trapping insulating film is used as storage information, and is read as a threshold of the transistor. The trapping insulating film refers to a charge-accumulable insulating film, and includes, for example, a silicon nitride film. Injection and emission of charge into/from such a charge accumulation region allows the threshold of the MISFET to be shifted so that the MISFET operates as a memory element. Such a flash memory includes a split gate cell using a metal-oxide-nitride-oxide-semiconductor (MONOS) film.
Publication of US Patent Application No. 2011/0001169 describes formation of a silicide layer on a surface of a fin in a FINFET.
Japanese Unexamined Patent Application Publication No. 2011-210790 describes that a silicide layer, which covers a surface of a source/drain region of a transistor having a channel region including a main surface of a semiconductor substrate, is formed through two heating steps, thereby abnormal growth of the silicide layer is prevented.
Japanese Unexamined Patent Application Publication No. 2006-041354 describes a split gate MONOS memory including a FINFET, in which a silicide layer covering the surface of a fin is provided.